1. Field of the Invention
The present invention generally relates to systems and methods for three-dimensional metrology and/or inspection of a specimen. Certain embodiments relate to systems and methods for metrology and inspection of a specimen such as a bumped wafer.
2. Description of the Relevant Art
Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a wafer. Additional examples of semiconductor fabrication processes may include, but are not limited to, chemical-mechanical polishing, etch, deposition, ion implantation, and electro-chemical plating. Multiple semiconductor devices may be fabricated in an arrangement on a wafer and then separated into individual semiconductor devices.
Prior to being separated into individual semiconductor devices, an entire wafer of semiconductor devices may be prepared for packaging. Packaging may include coupling a chip carrier such as a substrate to a semiconductor device. A chip carrier may provide mechanical strength, heat transfer, and environmental protection to a semiconductor device. In addition, a chip carrier may include electrical wiring or other electrical structures such that electrical connection may be made between a semiconductor device and another structure such as a card-on-board (“COB”) structure for a computer system. Preparing a wafer of semiconductor devices for packaging may include forming structures on a surface of the semiconductor devices that may be used to couple a semiconductor device to a chip carrier. For example, relatively small solder balls may be arranged in an area on a semiconductor device. Such relatively small solder balls may be commonly referred to as “bumps,” and a wafer on which such solder balls are formed may be commonly referred to as a “bumped wafer.” The solder balls may be configured to physically attach the semiconductor device to a chip carrier and to make electrical connection to a chip carrier. For example, a device may be placed on a substrate, and the solder balls may contact and melt onto an array of metal pads on the substrate. Such a packaging method may be commonly referred to as face-down bonding, flip-chip bonding, or controlled collapse chip connections (“C4”).
Bumps that are incorrectly formed on a wafer may cause significant problems during further processing such as probing of the wafer and during use of the device. For example, incorrectly formed bumps may damage probes on a probe card thereby causing tester downtime and incurring tester repair costs. Incorrectly formed bumps may also bridge power and ground contacts thereby resulting in excessive current draw through a probe card. Therefore, bumped wafers may typically be inspected and measured prior to probing. In addition, incorrectly formed bumps may not be detected during probing and may increase the potential for failure of a packaged device. Furthermore, probing may damage bumps especially on a wafer having a relatively high number of bumps per unit area that may require high vertical forces during testing to seat probes for proper contact. In this manner, inspection and metrology of a bumped wafer may also be performed after wafer probing.
Currently available methods for three-dimensional inspection, which may be commonly referred to as “defect detection,” and metrology of bumped wafers generally include first acquiring data in the x-y plane and then acquiring data in the z plane. Essentially, such systems may be described as being serial in data acquisition (i.e., two-dimensional (“2D”) data acquisition followed by three-dimensional (“3D”) data acquisition). For bumped wafers, 2D defects may include, for example, missing bumps, improperly located bumps, bridged bumps, large-diameter bumps, and small-diameter bumps. Examples of 3D defects may include, but are not limited to, bumps that may be too tall or too short or that may have protruding vertical spikes or recessed vertical pits. Because currently available methods are generally not capable of simultaneous 2D and 3D data acquisition, such methods may be significantly slower than either 2D or 3D data acquisition. In addition, 3D data acquisition may be significantly slower than 2D data acquisition thereby resulting in substantially reduced sampling for 3D in comparison to sampling for 2D. As used herein, the term “sampling” generally refers to the number of points or locations inspected or measured on a single specimen during a process. In other words, if a relatively large percentage of a wafer may be scanned to acquire x-y data, then only a much smaller percentage of the wafer may be scanned to acquire additional z data.
One currently available system, the ABI-2000 automatic bump inspection system, available from KLA-Tencor, San Jose, Calif., is configured to scan a wafer using bright field, white light imaging with image data captured using a charge coupled device (“CCD”) camera and a frame-grabber. A frame-grabber is a device that may be configured to receive a signal from a detector such as a CCD camera and to convert the signal (i.e., to digitize an image). In such a system, inspection and metrology algorithms are used to detect defects in the x-y plane and to make measurements in the x and y directions. Such a system is also configured to re-scan, or “revisit,” select locations on the wafer to acquire 3D data for individual bumps. This revisiting uses laser scanning microscopy and incremental z movement of the wafer along with additional algorithms to detect bump defects in the z plane and to make bump measurement in the z-direction.
In another example, systems developed and manufactured by Robotic Vision Systems, Inc., Canton, Massachusetts, e.g., Model Nos. WS-1000 and WS-2000, incorporate 2D vision technology using a time delay integration (“TDI”) camera and low-angle ring light or co-axial light. Such systems are configured to first scan a wafer to detect typical 2D bump defects and surface defects. Such systems are also configured to perform a second wafer scan using a laser triangulation technique to acquire 3D metrology measurements and to detect 3D bump defects. An example of a laser triangulation technique is illustrated in U.S. Pat. No. 6,181,472 to Liu, and is incorporated by reference as if fully set forth herein.
In yet another example, systems developed and manufactured by August Technology Corporation, Bloomington, Minn., e.g., the NSX bump inspection system, incorporate 2D vision technology using a high-resolution CCD camera and strobe illumination. Such systems are configured to first inspect a wafer to acquire 2D data for 2D defect detection of bumps and defect detection elsewhere on the surface of the wafer. For 3D data acquisition, relatively small, select regions of the wafer are revisited. At each of the smaller regions, the system may use automatic focusing at different vertical locations to determine the height of all bumps in the field of view.
Another example of a system for measuring 3D surface topography provides high resolution contour measurements of an object using interferometric methods. The system includes an optical head that is a moiré-type interferometer optical head employing co-sight detector phase shifting. Ronchi gratings are placed at image planes to produce moiré fringe patterns indicating the contour of the surface. The moiré images are relayed to detector planes, and CCD camera arrays view exactly the same image of the part except for the fringe pattern superimposed on the image. The images, and bucket images collected from a known reference surface needed to properly compensate the images and phase data, are used with a standard bucket phase algorithm. Output of the algorithm is analogous to the surface contour of the sample inspected. One example of such a system is illustrated in U.S. Pat. No. 6,268,923 B1 to Michniewicz et al., which is incorporated by reference as if fully set forth herein.
An additional example of a moiré-type system for 3D inspection of an object includes a source of light projected through a grid assembly. An image acquisition apparatus includes one or more cameras with an array of pixels in the form of a CCD camera. The system is used to simultaneously project at least three phase-shifted grids onto an object, to simultaneously take an image of each of the phase-shifted grids on the object, to gather an intensity value for each pixel of the images, and to compute the phase for each pixel of the image using the intensity images. The above steps are performed for a reference object and the object to be measured. The difference of height between the object and the reference object for every pixel is computed by using the respective phases for each pixel, and the relief of the object for each pixel is determined using the difference of height at every pixel. An example of such a system is illustrated in U.S. Patent Application Publication No. US 2002/0018118 A1 to Coulombe et al. and PCT International Publication No. WO 01/71279 A1 to Coulombe et al., which are incorporated by reference as if fully set forth herein.
There are several disadvantages to the moiré-type systems and methods for three-dimensional inspection of objects. For example, these systems and methods include complex system configurations and rely on data collected from a separate reference object. Therefore, the methods have a lower throughput than methods that do not require a separate reference. In addition, the systems measure and use a sine wave pattern to determine the surface contour or relief of the object. Therefore, the sensitivity of the system may vary for objects of different heights. For example, the system may be more sensitive to measurements that correspond to a slope of the sine wave pattern than to measurements that correspond to a crest or valley of the sine wave pattern. In addition, using such a sine wave pattern may yield inaccurate height measurements. For example, the period of the sine wave pattern may be selected to correspond to a range of expected heights. However, if the height of an object is outside of this range, the height of the object may be inaccurately reported with an error of one or more times the range of heights.
There are several additional disadvantages to currently available systems and methods for three-dimensional inspection of bumped wafers. For example, as described above, such systems are configured to scan a wafer more than once in series to acquire 2D and 3D data for inspection and metrology. In addition, configurations of such systems are incompatible with rapid scanning of relatively large areas of bumped wafers. Such disadvantages will generally lower a throughput of an inspection and metrology system. Furthermore, such systems may be relatively complex due to the use of separate 2D and 3D data acquisition and processing systems. This disadvantage will generally increase cost and reduce reliability of an inspection and metrology system.